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HT9170 DTMF Receiver
Features
* * * * *
Operating voltage: 2.5V~5.5V Minimal external components No external filter is required Low standby current (on power down mode) Excellent performance
* * * *
Tristate data output for mC interface 3.58MHz crystal or ceramic resonator 1633Hz can be inhibited by the INH pin HT9170B: 18-pin DIP package HT9170D: 18-pin SOP package
General Description
The HT9170 series are Dual Tone Multi Frequency (DTMF) receivers integrated with digital decoder and bandsplit filter functions. The H T 9 1 7 0 B a nd H T 9 1 7 0 D t y p es s u p p l y power-down mode and inhibit mode operations. All types of the HT9170 series use digital counting techniques to detect and decode all the 16 DTMF tone pairs into a 4-bit code output. Highly accurate switched capacitor filters are employed to divide tone (DTMF) signals into low and high group signals. A built-in dial tone rejection circuit is provided to eliminate the need for pre-filtering.
Selection Table
Function Operating OSC Tristate Power 1633Hz Voltage Frequency Data Output Down Inhibit Part No. HT9170B HT9170D 2.5V~5.5V 2.5V~5.5V 3.58MHz 3.58MHz O O O O O O DV DVB Package O O 3/4 3/4 18 DIP 18 SOP
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Block Diagram
PW DN X2 X1 3 .5 8 M H z C ry s ta l O s c illa to r B ia s C ir c u it V re f G e n e ra to r S te e r in g C o n tr o l C ir c u it VREF R T /G T EST DV DVB
Low VP VN GS OPA P r e - F ilte r
G ro u p F ilte r
F re q u e n c y D e te c to r
Code D e te c to r
H ig h G r o u p F ilte r
L a tc h & O u tp u t B u ffe r
D0 D1 D2 D3
IN H
OE
Pin Assignment
VP 1 2 3 4 5 6 7 8 9 VN GS VREF IN H PW DN X1 X2 VSS 18 17 16 15 14 13 12 11 10 VDD R T /G T EST DV D3 D2 D1 D0 OE VP 1 2 3 4 5 6 7 8 9 VN GS VREF IN H PW DN X1 X2 VSS 18 17 16 15 14 13 12 11 10 VDD R T /G T EST DV D3 D2 D1 D0 OE
HT9170B 1 8 D IP
HT9170D 18 SO P
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Pin Description
Pin Name I/O VP VN GS VREF X1 X2 I I O O I O OSCILLATOR VREF Internal Connection Description
OPERATIONAL Operational amplifier non-inverting input AMPLIFIER Operational amplifier inverting input Operational amplifier output terminal Reference voltage output, normally VDD/2 The system oscillator consists of an inverter, a bias resistor and the necessary load capacitor on chip. A standard 3.579545MHz crystal connected to X1 and X2 terminals implements the oscillator function. Active high. This enables the device to go into power down mode and inhibits the oscillator. This pin input is internally pulled down. Logic high. This inhibits the detection of tones representing characters A, B, C and D. This pin input is internally pulled down. Negative power supply D0~D3 output enable, high active Receiving data output terminals OE=H: Output enable OE=L: High impedance Data valid output When the chip receives a valid tone (DTMF) signal, the DV goes high; otherwise it remains low. Early steering output (see Functional Description) Tone acquisition time and release time can be set through connection with external resistor and capacitor. Positive power supply, 2.5V~5.5V for normal operation One-shot type data valid output, normal high, when the chip receives a valid time (DTMF) signal, the DVB goes low for 10ms.
PWDN
I
CMOS IN Pull-low CMOS IN Pull-low 3/4 CMOS IN Pull-high CMOS OUT Tristate CMOS OUT CMOS OUT CMOS IN/OUT 3/4 CMOS OUT
INH VSS OE D0~D3
I 3/4 I O
DV EST RT/GT VDD DVB
O O I/O 3/4 O
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Approximate internal connection circuits
O P E R A T IO N A L A M P L IF IE R VREF
X1 VN VP
VOPA V+
O S C IL L A T O R
X2
C M O S IN P u ll- h ig h
EN
CMOS OUT T r is ta te
GS
OPA
20pF
10M
10pF
CMOS OUT
C M O S IN /O U T
C M O S IN P u ll- lo w
Absolute Maximum Ratings
Supply Voltage.................................-0.3V to 6V Input Voltage .................VSS-0.3V to VDD+0.3V Storage Temperature.................-50C to 125C Operating Temperature ..............-20C to 75C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD ISTB VIL VIH IIL IIH ROE RIN Parameter Operating Voltage Operating Current Standby Current Low Input Voltage High Input Voltage Low Input Current High Input Current Pull-high Resistance (OE) Input Impedance (VN, VP) Test Conditions VDD 3/4 5V 5V 5V 5V 5V 5V 5V 5V Conditions 3/4 3/4 PWDN=5V 3/4 3/4 VVP=VVN=0V VVP=VVN=5V VOE=0V 3/4 Min. 2.5 3/4 3/4 3/4 4.0 3/4 3/4 60 3/4 Typ. 5 3.0 10 3/4 3/4 3/4 3/4 100 10 Max. 5.5 7 25 1.0 3/4 0.1 0.1 150 3/4
Ta=25C Unit V mA mA V V mA mA kW MW
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Symbol IOH IOL fOSC Parameter Source Current (D0~D3, EST, DV) Sink Current (D0~D3, EST, DV) System Frequency Test Conditions VDD 5V 5V 5V Conditions VOUT=4.5V VOUT=0.5V Min. -0.4 1.0 Typ. -0.8 2.5 Max. 3/4 3/4 Unit mA mA MHz
Crystal=3.5795MHz 3.5759 3.5795 3.5831
A.C. Characteristics
Symbol DTMF Signal Input Signal Level Twist Accept Limit (Positive) Twist Accept Limit (Negative) Dial Tone Tolerance Noise Tolerance Third Tone Tolerance Frequency Deviation Acceptance Frequency Deviation Rejection Power Up Time (tPU) (See Figure 4.) Gain Setting Amplifier RIN IIN VOS PSRR CMRR AVO fT VOUT Input Resistance Input Leakage Current Offset Voltage Power Supply Rejection Common Mode Rejection Open Loop Gain Gain Band Width Output Voltage Swing 5V 5V 5V 5V 5V 5V 5V 5V 3/4 VSS<(VVP,VVN)100kW 3V 5V 5V 5V 5V 5V 5V 5V 5V 5V Parameter Test Conditions VDD Conditions
fOSC=3.5795MHz, Ta=25C Min. Typ. Max. Unit
-36 -29 3/4 3/4 3/4 3/4 3/4 3/4 3.5 3/4
3/4 3/4 10 10 18 -12 -16 3/4 3/4 30
-6 1 3/4 3/4 3/4 3/4 3/4 1.5 3/4 3/4
dBm dB dB dB dB dB % % ms
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
10 0.1 25 60 60 65 1.5 4.5
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
MW mA mV dB dB dB MHz VPP
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Symbol RL CL VCM tDP tDA tACC tREJ tIA tIR tPDO tPDV tDOV tDDO tEDO Parameter Load Resistance (GS) Load Capacitance (GS) Common Mode Range Tone Present Detection Time Tone Absent Detection Time Acceptable Tone Duration Rejected Tone Duration Acceptable Inter-digit Pause Rejected Inter-digit Pause Propagation Delay (RT/GT to DO) Propagation Delay (RT/GT to DV) Output Data Set Up (DO to DV) Disable Delay (OE to DO) Enable Delay (OE to DO) Test Conditions VDD 5V 5V 5V No load Conditions 3/4 3/4 Min. Typ. Max. Unit 3/4 3/4 3/4 5 3/4 3/4 20 3/4 20 3/4 3/4 3/4 3/4 3/4 50 100 3.0 16 4 3/4 3/4 3/4 3/4 8 12 4.5 300 50 3/4 3/4 3/4 22 8.5 42 3/4 42 3/4 11 3/4 3/4 3/4 60 kW pF VPP ms ms ms ms ms ms ms ms ms ns ns
Steering Control
Note: DO=D0~D3
V 1 2 3 100kW 5 3 .5 7 9 5 4 5 M H z 7 8 20pF 20pF VSS 9 6 4 VP VN GS VREF (IN H ) (P W D N ) X1 X2 VSS VDD R T /G T EST DV D3 D2 D1 D0 OE 18 17 16 15 14 13 12 11 10 300kW
DD
0 .1 m F
Tone 0 .1 m F
100kW
H T 9 1 7 0 /B /D
Figure 1. Test circuit
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Functional Description
Overview The HT9170 series tone decoders consist of three band pass filters and two digital decode circuits to convert a tone (DTMF) signal into digital code output. An operational amplifier is built-in to adjust the input signal (refer to Figure 2).
C V
i
Steering control circuit The steering control circuit is used for measuring the effective signal duration and for protecting against drop out of valid signals. It employs the analog delay by external RC time-constant controlled by EST. The timing is shown in Figure 3. The EST pin is normally low and draws the RT/GT pin to keep low through discharge of external RC. When a valid tone input is detected, EST goes high to charge RT/GT through RC. When the voltage of RT/GT changes from 0 to VTRT (2.35V for 5V supply), the input signal is effective, and the correct code will be created by the code detector. After D0~D3 are completely latched, DV output becomes high. When the voltage of RT/GT falls down from VDD to VTRT (i.e.., when there is no input tone), DV output becomes low, and D0~D3 keeps data until a next valid tone input is produced. By selecting adequate external RC value, the minimum acceptable input tone duration (tACC) and the minimum acceptable inter-tone rejection (tIR) can be set. External components (R, C) are chosen by the formula (refer to Figure 5.): tACC=tDP+tGTP; tIR=tDA+tGTA; where tACC: Tone duration acceptable time tDP: EST output delay time (L(R)H) tGTP: Tone present time tIR: Inter-digit pause rejection time tDA: EST output delay time (H(R)L) tGTA: Tone absent time
R1
VP VN
RF
GS VREF
HT9170 S e r ie s
( a ) S ta n d a r d in p u t c ir c u it
V V C
i1 i2
R1
VP VN
C
R2 R3 R4 R5 GS VREF
HT9170 S e r ie s
( b ) D iffe r e n tia l in p u t c ir c u it
Figure 2. Input operation for amplifier application circuits The pre-filter is a band rejection filter which reduces the dialing tone from 350Hz to 400Hz. The low group filter filters low group frequency signal output whereas the high group filter filters high group frequency signal output. Each filter output is followed by a zero-crossing detector with hysteresis. When each signal amplitude at the output exceeds the specified level, it is transferred to full swing logic signal. When input signals are recognized to be effective, DV becomes high, and the correct tone code (DTMF) digit is transferred.
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Timing Diagrams
tR Tone tD
P EJ
t IA Tone n tD
P
t IR Tone n+1
tD
A
tD
P
EST tA V
CC
R T /G T
TRT
tG tP
DO
TP
tG
TA
D 0~D 3
Tone C ode n tP
DV
1 tD
Tone C ode n
OV
Tone C ode n+1 tP
DV
DV tD OE
DO
tE
DO
Figure 3. Steering timing
Tone
Tone
PW DN
EST tP
U
Figure 4. Power up timing
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V
DD
V
DD
HT9170 S e r ie s
VDD C R T /G T EST R
HT9170 S e r ie s
VDD C R T /G T EST D1 R1 R2
(a) Fundamental circuit: tGTP = R C Ln (VDD / (VDD - VTRT)) tGTA = R C Ln (VDD / VTRT)
V
DD
(c) tGTP > tGTA : tGTP = R1 C Ln (VDD / (VDD - VTRT)) tGTA = (R1 // R2) C Ln (VDD / VTRT)
HT9170 S e r ie s
VDD C R T /G T EST D1 R1 R2
(b) tGTP < tGTA : tGTP = (R1 // R2) C Ln (VDD - VTRT)) tGTA = R1 C Ln (VDD / VTRT) Figure 5. Steering time adjustment circuits DTMF dialing matrix
CO L1 CO L2 ROW 1 ROW 2 ROW 3 ROW 4 7 8 9 C # D 0 * 4 5 6 B 1 2 3 A CO L3 CO L4
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DTMF data output table Low Group (Hz) 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 3/4 Z: High impedance Data output The data outputs (D0~D3) are tristate outputs. When OE input becomes low, the data outputs (D0~D3) are high impedance. High Group (Hz) 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 3/4 Digit 1 2 3 4 5 6 7 8 9 0 * # A B C D ANY OE H H H H H H H H H H H H H H H H L D3 L L L L L L L H H H H H H H H L Z D2 L L L H H H H L L L L H H H H L Z D1 L H H L L H H L L H H L L H H L Z D0 H L H L H L H L H L H L H L H L Z
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Application Circuits
V 1 2 3 100kW 5 T o o th e r d e v ic e 7 X 'T A L 9 C1 C2 VSS 8 6 4 VP VN GS VREF IN H PW DN X1 X2 VSS VDD R T /G T EST DV D3 D2 D1 D0 OE 18 17 16 15 14 13 12 11 10 T o o th e r d e v ic e 300kW
DD
0 .1 m F
DTM F 0 .1 m F
100kW
H T 9 1 7 0 B /D 1 8 D IP /S O P
N o t e : ( a ) X 'T A L = 3 . 5 7 9 5 4 5 M H z c r y s t a l C1 = C2 @ 20pF ( b ) X 'T A L = 3 . 5 8 M H z c e r a m ic r e s o n a t o r C1 = C2 @ 39pF
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Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright O 1999 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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